#ifndef __FH_GMAC_PLAT_H__
#define __FH_GMAC_PLAT_H__
#include <linux/phy.h>

#define FH_GMAC_PHY_IP101G	0x02430C54
#define FH_GMAC_PHY_RTL8201	0x001CC816
#define FH_GMAC_PHY_TI83848	0xFFFFFFFF
#define FH_GMAC_PHY_INTERNAL 0x441400
#define FH_GMAC_PHY_DUMMY	0xE3FFE3FF
#define FH_GMAC_PHY_INTERNAL_V2 0x46480000
#define FH_GMAC_PHY_INTERNAL_V3 0x00568101
#define FH_GMAC_PHY_RTL8211F 0x001cc916
#define FH_GMAC_PHY_MAE0621 0x7b744411
#define FH_GMAC_PHY_JL2101 0x937c4032
struct phy_interface_info{
	/*internal or external phy*/
	u32 phy_sel;
	/*mii phy or rmii phy*/
	u32 phy_inf;

	void (*phy_reset)(void);
	int (*sync_mac_spd)(unsigned int spd);
#define PHY_TRIGER_OK	0
#define PHY_TRIGER_ERR	1
	int (*phy_triger)(void);
	int (*ex_sync_mac_spd)(unsigned int spd, void* pri);
	void (*brd_link_up_cb)(void* pri);
	void (*brd_link_down_cb)(void* pri);
	void (*dll_set)(u32 tx_val, u32 rx_val);
	void (*polarity_set)(u32 tx_pol, u32 rx_pol);
};

#define W_PHY	0x01
#define M_PHY	0x02
#define ACTION_MASK	0xff
struct phy_reg_cfg_list{
	u32 r_w;
	u32 reg_add;
	u32 reg_val;
	u32 reg_mask;
};
#define MAX_PHY_REG_SIZE	64
#define DLL_SETTING_ENABLE	0x55aaaa55
struct phy_reg_cfg {
	u32 id;
	struct phy_reg_cfg_list list[MAX_PHY_REG_SIZE];
	/*phy interface bind here better, phy support set here*/
	u32 inf_sup;

	u32 dll_enable;
	//10m / 100m / 1000m
	u32 tx_10_dll_val;
	u32 rx_10_dll_val;
	u32 tx_100_dll_val;
	u32 rx_100_dll_val;
	u32 tx_1000_dll_val;
	u32 rx_1000_dll_val;
	//here maybe set 1000M/100M/10M pll better..
	u32 tx_1000_polarity;
	u32 rx_1000_polarity;
	u32 tx_100_polarity;
	u32 rx_100_polarity;
	u32 tx_10_polarity;
	u32 rx_10_polarity;
};

struct s_train_val{
	u8 *name;
	u32 src_add;
	u32 src_mask;
	u32 src_vaild_index;
	u8 *dst_base_name;
	u32 dst_add;
	u32 dst_vaild_index;
	u32 *bind_train_array;
	u32 bind_train_size;
	int usr_train_offset;
};

#define DLL_POL_FWD 0
#define DLL_POL_REV 1
#define DLL_ID_MASK	0x00ffffff
struct soc_reg_tuning{
	//phy id 0 ~ 23bit
	unsigned char id_l;
	unsigned char id_m;
	unsigned char id_h;
	//1000_txpol:1000_rxpol:100_txpol:100_rxpol
	unsigned char	area_pol;

	unsigned char	area_1000_txdll;
	unsigned char	area_1000_rxdll;
	unsigned char	area_100_txdll;
	unsigned char	area_100_rxdll;
};


struct fh_gmac_platform_data {
	u32 phy_reset_pin;
	void (*gmac_reset)(void);
	/* phy need to sel func */
	int (*phy_sel)(unsigned int sel);
	//mac need set mii or rmii to adjust phy, here just bind to phy driver
	int (*inf_set)(unsigned int inf);
	struct phy_interface_info phy_info[2];
	void *p_cfg_array;
};

#endif
